This invention relates generally to field-effect transistors ("FETs"), and more particularly to those FETs having a channel region that is generally vertical with respect to the horizontal plane of the silicon wafer.
As the performance and complexity of integrated circuits, and in particular memory circuits, increases, the area of an individual transistor on the integrated circuit must decrease in order to maintain die size and to control manufacturing costs. In the past, vertical FETs were introduced either in a trench or a V-groove to align the channel region of the FET vertically. Therefore, the area of the FET could be reduced because the channel did not use valuable horizontal area leading to a larger die area. A problem with many of the vertical designs is that performance is sacrificed as the area is decreased. Parasitic capacitance from the gate of the FET to the source ("overlap capacitance"), drain, or substrate can increase in the vertical FET, which results in a lower maximum operating frequency. In addition, in many vertical designs, the drain contact is made at the bottom of the FET through the substrate or by directly metallizing the bottom surface of the die, and thus the drain and source contacts cannot both be made at the surface of the transistor.
Accordingly, a need remains for a vertical FET having an area smaller than a horizontal FET having a comparable channel region, while having minimum gate parasitic capacitance and the option of surface gate, source, and drain contacts.